A circuit design may be presented using functionally equivalent, though different, representations. The different representations may be considered as being of different abstraction levels. One example of functionally equivalent representations is pre-synthesis and post-synthesis designs.
The process of synthesizing logic given in Register Transfer Level (RTL) description into a placed-and-routed circuit description involves numerous steps, in which many transformations are often applied to the design netlist. Specifically, these may include logic optimization in which various techniques are used for optimizing the design for desired objective functions, usually reducing delay and area. Logic optimization techniques can range from simple equivalent gate merging, to logic refactoring and rewriting and even more aggressive reduction and optimization methods. A common side effect of those optimization techniques is that signal names and the original logic structure are not necessarily preserved throughout the process, and usually the final design netlist is much different than the initial netlist in this regard. As a result any task which involves using the post-synthesis data to analyze behavior, bugs or any kind of problem in the high-level RTL descriptions is problematic as it is usually hard to establish a correlation between the post-synthesis data and the original RTL representation.
The circuit designs may have corresponding input and output elements. Input elements include primary inputs of the circuit as well as output signals of memory elements, such as latches and flip-flops, based on which the combinational logic of the circuit design is applied to define outputs in each cycle. Output elements include primary outputs of the circuit as well as input signals of the memory elements. Though the circuits may differ in the signals used and in the combinational logic implementations, they may preserve correlations between the primary inputs, primary outputs and memory elements. In addition, the circuits may be functionally equivalent so they require that each output element would provide the same function in both designs.